1. Field of the Invention
This invention relates to a semiconductor device containing bipolar transistors, such as a logic circuit using Bi-CMOS (a circuit composed of bipolar transistors and complementary MOS transistors).
2. Description of the Related Art
Logic gate circuits composed of Bi-CMOS circuits, or Bi-CMOS logic gate circuits, are widely used because of the high operating speed and low power consumption.
FIG. 8 shows a Bi-CMOS circuit, which contains a P-channel MOS transistor 11 and an N-channel MOS transistor 12, the gate electrodes of both transistors being supplied with an input signal. The source of the P-channel MOS transistor 11 is connected to a power supply V.sub.CC' while the drain of the transistor 11 is connected via a resistor 13 to the drain of the N-channel MOS transistor 12, whose source is connected via a resistor 14 to the ground. The drain of each of MOS transistors 11 and 12 is connected to the base of each of NPN bipolar transistors 15 and 16, respectively. This arrangement of MOS transistors 11 and 12, bipolar transistors 15 and 16, and resistor 13 and 14 provides an inverter circuit.
In this inverter circuit, the resistor 13 (14) is connected across the base and emitter terminals of the NPN bipolar transistor 15 (16) as shown by a broken line.
FIG. 9 shows a layout pattern of Bi-CMOS circuitry with the above-mentioned arrangement on a semiconductor wafer 20. First set on this wafer 20 is an area 21 forming a basic CMOS cell, in which the P-channel MOS transistor 11 and N-channel MOS transistor 12 are formed. On both sides of the basic cell area 21, transistor areas 22 and 23, each forming bipolar transistors 15 and 16, are placed. Located adjacent to the transistor areas 22 and 23 are resistor areas 26 and 27 where resistor 13 and 14 are formed with diffused resistors 24 and 25.
That is, the bipolar transistors 15 and 16 are formed in places different from places in which resistors 13 and 14 are formed. The reason for making the resistors 13 and 14 of the diffused resistors 24 and 25 is to lower production costs.
The arrangement of the NPN bipolar transistors 15 and 16 and resistors 13 and 14 in separate places involves larger pattern areas for the diffused resistors 24 and 25, which, in turn, need separate well areas in which the areas 26 and 27 are set, resulting in the larger circuit layout area.